Sigma-delta converters, generally also called sigma-delta modulators or ΣΔ modulators, are used for many applications particularly in the field of analog-digital conversion. Another use is actuating regulatable frequency divider circuits in a phase locked loop. The use of a sigma-delta modulator for actuation in a phase locked loop is shown in prior art FIG. 9.
The phase locked loop shown contains a phase detector PD, with a charge pump CP connected to it, and also a voltage-controlled oscillator VCO. A return path in the phase locked loop contains a regulatable frequency divider :N which has its control input connected to a sigma-delta modulator ΣΔ. The sigma-delta modulator ΣΔtakes a supplied digital data word F with a high bit length, for example a data word F with a length n of n=24 bits, and generates a time-altered representation of the data word with a much lower resolution, for example with a bit length n′=3.
The regulatable frequency divider can therefore switch to and fro between various divider values N, the middle divider value representing a value which corresponds to a word F which is supplied to the modulator and is a broken fraction. A sigma-delta converter can therefore also be understood to be an interpolator which delivers a digital output signal with a low bit resolution, said output signal representing an input signal with a high bit resolution.
To reduce the quantization noise and to increase the resolution, modern sigma-delta modulators have a pronounced noise shaping response. Prior art FIG. 8 shows a sigma-delta modulator with low quantization noise, which is achieved by cascading a plurality of series-connected individual modulator stages.
A cascaded sigma-delta modulator of this kind is also called a MASH modulator, for Multi Stage Noise Shaping modulator. The third-order MASH modulator shown in prior art FIG. 8 contains three series-connected individual modulator stages S1 to S3. In this case, each modulator stage has an accumulator A1 whose sum output s is fed back to an input b of the respective accumulator A1 via a flipflop F1. In addition, each accumulator in the individual modulator stages S1 to S3 has its output side connected to the input a of the accumulator A1 in the following stage.
The individual accumulators A1 in the three series-connected stages produce a sum from the data words supplied to their inputs a and b and output this sum at their outputs s. The individual accumulators have a processing width of 2b bits, that is to say that the supplied data word has the bit length b. If the sum overflows, an overflow signal is produced at the overflow output c.
The overflow signal is supplied to a return path containing the summators E1 and E2. At their outputs, the two summators E1 and E2 output the 3-bit output signal Y(k). This may cover the value range −3, . . . , +4.
The output signal Y(k) from a third-order sigma-delta modulator can also be described mathematically by a sum for the individual output elements. Hence:Y(k)=Y1(k)+Y2(k)*(1−k−1)+Y3(k)*(1−k−1)2Y(k)=F(k)+E3(k)*(1−k−1)3
Here, Y1(k), Y2(k), Y3(k) denote the output signals from the first, second and third accumulator stages and E3(k) denotes the quantization error in the third modulator stage S3 of the sigma-delta modulator.
However, the sigma-delta modulator has only limited suitability for very rapid conversions or a high processing speed. The reason for this, inter alia, is that the known topology shown in prior art FIG. 9 results in a total delay time τtot which is made up of the sum of the delay times for the individual accumulators plus the sum of the delay times for the summators E1 and E2. The delay in the individual components is in turn a result of the manufacturing technology used. In principle, the maximum signal processing speed is thus limited to the total delay time for the modulator shown.